Description: crc_table.c is for reset seed( 0000 )
crc_table_1.c is for reset seed( ffff)
CRC16_D8_m.v is a verilog module of byte paralle crc.
CRC16_D8_m_tb.v is the testbench file of above module. Platform: |
Size: 3242 |
Author:樊文杰 |
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Description: crc_table.c is for reset seed( 0000 )
crc_table_1.c is for reset seed( ffff)
CRC16_D8_m.v is a verilog module of byte paralle crc.
CRC16_D8_m_tb.v is the testbench file of above module. -crc_table.c is for reset seed (0000) crc_table_1.c is for reset seed (ffff) CRC16_D8_m.v is a verilog module of byte paralle crc.CRC16_D8_m_tb.v is the testbench file of above module. Platform: |
Size: 3072 |
Author:樊文杰 |
Hits:
Description: 关于CRC的发射，以及接受的验证，用Verilog实现，包含testbench验证-About CRC launch, as well as acceptable verification, using Verilog implementation, including verification testbench Platform: |
Size: 4506624 |
Author:尹腾飞 |
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